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| STR750F ARM7TDMI-STM 32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN Core - ARM7TDMI-S 32-bit RISC CPU - 54 DMIPS @ 60 MHz Memories - Up to 256 KB Flash program memory (10k erase/write cycles, retention 20 yrs at 85C) - 16KB Read-While-Write Flash for data (100k erase/write cycles, retention 20 yrs@ 85C) - Flash Data Readout and Write Protection - 16KBytes embedded high speed SRAM - Memory mapped interface (SMI) to ext. Serial Flash (64 MB) w. boot capability Clock, Reset and Supply Management - Single supply 3.3V 10% or 5V 10% - Embedded 1.8V Voltage Regulators with Low Power features - Smart Clock Controller with flexible clock generation capability: - Internal RC for fast start-up and backup clock mechanism - Up to 60 MHz operation using internal PLL with 4 or 8 MHz crystal/ceramic osc. - Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers - Real Time Clock, driven by low power internal RC or 32.768 kHz dedicated osc, for clock-calendar and Auto Wake-up Nested interrupt controller - Fast interrupt handling with 32 vectors - 16 IRQ priorities, 2 maskable FIQ sources - 16 external interrupt / wake-up Lines DMA - 4-channel DMA controller - Circular buffer management - Support for UART, SSP, Timers, ADC 6 Timers - 16-bit watchdog timer (WDG) LQFP64 10x10 mm LQFP100 14 x 14 mm LFBGA64 8 x 8 x 1.7 mm LFBGA100 10 x 10 x 1.7 mm - 16-bit timer for system timebase functions - 3 synchronizable timers each with up to 2 input captures and 2 output compare/PWMs. - 16-bit 6-channel synchronizable PWM timer - Dead time generation, edge/center-aligned waveforms and emergency stop - Ideal for induction/brushless DC motors 8 Communications Interfaces - 1 I2C interface - 3 HiSpeed UARTs w. Modem/LIN capability - 2 SSP interfaces (SPI or SSI) up to 16 Mb/s - 1 CAN interface (2.0B Active) - 1 USB full-speed 12 Mb/s interface with 8 configurable endpoint sizes 10-bit A/D Converter - 16/11 chan. with prog. Scan Mode & FIFO - Programmable Analog Watchdog feature - Conversion: min. 3.75 s, range: 0 to VDD_IO - Start conversion can be triggered by timers Up to 72/38 I/O ports - 72/38 GPIO lines with High Sink capabilities - Atomic bit SET and RES operations October 2006 Rev 2 1/71 www.st.com 1 Contents STR750F Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.0.1 Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Supply Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O characteristics versus the various power schemes (3.3V or 5.0V) . 28 Current Consumption Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1 3.2.2 3.2.3 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 3.3.11 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33 Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2/76 STR750F 3.3.12 Contents 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3/76 Introduction STR750F 1 Introduction This Datasheet contains the description of the STR750 family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information. For complete information on the Microcontroller memory, registers and peripherals. Please refer to the STR750 Reference Manual. For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical Reference Manual available from Arm Ltd. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on third-party development tools, please refer to the http://www.st.com/mcu website. Table 1. Device summary STR755FRx STR751FRx STR752FRx 64K/128K/256K 16K RWW 16K -40 to +85C / -40 to +105C (see Table 44) 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 38 I/Os 13 Wake-up lines, 11 A/D Channels 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 72 I/Os 15 Wake-up lines, 16 A/D Channels None 3.3V or 5V T=LQFP100 14x14, H=LFBGA100 USB+CAN STR755FVx STR750FVx Features Flash - Bank 0 (bytes) Flash - Bank 1 (bytes) RAM (bytes) Operating Temp. Common Peripherals USB/CAN peripherals Operating Voltage Packages (x) None 3.3V or 5V USB 3.3V CAN T=LQFP64 10x10, H=LFBGA64 4/71 STR750F Introduction 1.1 Overview The STR750 family includes devices in 2 package sizes: 64-pin and 100-pin. Both types have the following common features: ARM7TDMI-STM core with embedded Flash & RAM STR750 family has an embedded ARM core and is therefore compatible with all ARM tools and software. It combines the high performance ARM7TDMI-STM CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip highspeed single voltage FLASH memory and high-speed RAM. Figure 1 shows the general block diagram of the device family. Embedded Flash Memory Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data. An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to be erased/programmed on-the-fly. This partitioning feature is ideal for storing application parameters. When configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states for sequential accesses and 1 wait state for random access (maximum 60 MHz). When not configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states (maximum 32 MHz) Embedded SRAM 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Enhanced Interrupt Controller (EIC) In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt controller able to handle up to 32 vectors and 16 priority levels. This additional hardware block provides flexible interrupt management features with minimal interrupt latency. Serial Memory Interface (SMI) The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It communicates at a speed of up to 48 MHz. It can be used to access data, execute code directly or boot the application from external memory. The memory is addressed as 4 banks of up to 16 Mbytes each. Clocks and start-up After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its stabilization time is monitored using a dedicated counter. An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the circuit automatically switches to the FREEOSC oscillator and an interrupt is generated. In Run mode, the AHB and APB clock speeds can be set at a large number of different frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32 MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM). 5/71 Introduction In SLOW mode, the AHB clock can be significantly decreased to reduce power consumption. STR750F The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the APB peripherals. Boot modes At start-up, boot pins are used to select one of five boot options: Boot from internal flash Boot from external serial Flash memory Boot from internal boot loader Boot from internal SRAM Booting from SMI memory allows booting from a serial flash. This way, a specific boot monitor can be implemented. Alternatively, the STR750F can boot from the internal boot loader that implements a boot from UART. Power Supply Schemes You can connect the device in any of the following ways depending on your application. Power Scheme 1: Single external 3.3V power source. In this configuration the VCORE supply required for the internal logic is generated internally by the main voltage regulator and the VBACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 3.3V power source. Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. VCORE is provided externally through the V18 and V18REG power pins and VBACKUP through the V18_BKP pin. This scheme is intended to save power consumption for applications which already provide an 1.8V power supply. Power Scheme 3: Single external 5.0V power source. In this configuration the VCORE supply required for the internal logic is generated internally by the main voltage regulator and the VBACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 5.0V power source. Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. VCORE is provided externally through the V18 and V18REG power pins and VBACKUP through the V18_BKP pin. This scheme is intended to provide 5V I/O capability. Caution: When powered by 5.0V, the USB peripheral cannot operate. 6/71 STR750F Introduction Low Power modes The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY. SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main oscillator can be stopped and the device is driven by a low power clock (fRTC). The clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator. PCG MODE (Peripheral Clock Gating MODE): When the peripherals are not used, their APB clocks are gated to optimize the power consumption. WFI MODE (Wait For Interrupts): only the CPU clock is stopped, all peripherals continue to work and can wake-up the CPU when IRQs occur. STOP MODE: all clocks/peripherals are disabled. It is also possible to disable the oscillators and the Main Voltage Regulator (In this case the VCORE is entirely powered by V18_BKP). This mode is intended to achieve the lowest power consumption with SRAM and registers contents retained. The system can be woken up by any of the external interrupts / wake-up lines or by the RTC timer which can optionally be kept running. The RTC can be clocked either by the 32.768 kHz Crystal or the Low Power RC Oscillator. Alternatively, STOP mode gives flexibility to keep the either main oscillator, or the Flash or the Main Voltage Regulator enabled when a fast start after wake-up is preferred (at the cost of some extra power consumption). STANDBY MODE: This mode (only available in single supply power schemes) is intended to achieve the lowest power consumption even when the temperature is increasing. The digital power supply (VCORE) is completely removed (no leakage even at high ambient temperature). SRAM and all register contents are lost. Only the RTC remains powered by V18_BKP. The STR750F can be switched back from STANDBY to RUN mode by a trigger event on the WKP_STDBY pin or an alarm timeout on the RTC counter. Caution: It is important to bear in mind that it is forbidden to remove power from the VDD_IO power supply in any of the Low Power Modes (even in STANDBY MODE). DMA The flexible 4-channel general-purpose DMA is able to manage memory to memory, peripheral to memory and memory to peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. The DMA can be used with the main peripherals: UART0, SSP0, Motor control PWM timer (PWM), standard timer TIM0 and ADC. RTC (Real Time Clock) The real time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated. WDG (Watchdog Timer) The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as watchdog to reset the device when a problem occurs, or as free running timer for application time out management. 7/71 Introduction STR750F Timebase Timer (TB) The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O pins. It can be used for software triggering, or to implement the scheduler of a real time operating system. Synchronizable Standard Timers (TIM2:0) The three standard timers are based on a 16-bit auto-reload counter and feature up to 2 input captures and 2 output compares (for external triggering or time base / time out management). They can work together with the PWM timer via the Timer Link feature for synchronization or event chaining. In reset state, timer Alternate Function I/Os are connected to the same I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices, timer Alternate Function I/Os can be connected, or "remapped", to other I/O ports as summarized in Table 2 and detailed in Table 5. This remapping is done by the application via a control register. Table 2. Standard timer alternate function I/Os Number of Alternate Function I/Os Standard Timer Functions 100-pin package Input Capture TIM 0 Output Compare/PWM Input Capture TIM 1 Output Compare/PWM Input Capture TIM 2 Output Compare/PWM 2 1 2 2 2 1 2 1 2 2 2 1 1 2 1 2 64-pin package Default mapping 1 Remapped 2 Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is mapped to a DMA channel. Motor Control PWM timer (PWM) The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6 channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or centre-aligned patterns and supports dead-time insertion. It has many features in common with the standard TIM timers which has the same architecture and it can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM timer is mapped to a DMA channel. IC bus The IC bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz). 8/71 STR750F Introduction High Speed Universal Asynch. Receiver Transmitter (UART) The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 16 bytes each have been implemented. One UART can be served by the DMA controller (UART0). Synchronous Serial Peripheral (SSP) The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave device. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the Motorola SPI or TI SSI protocols. One SSP can be served by the DMA controller (SSP0). Controller Area Network (CAN) The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously. Universal Serial Bus (USB) The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL. VDD must be in the range 3.3V10% for USB operation. ADC (Analog to Digital Converter) The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in 64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is performed on a selected group of analog inputs. The minimum conversion time is 3.75 s (including the sampling time). The ADC can be served by the DMA controller. An analog watchdog feature allows you to very precisely monitor the converted voltage of up to four channels. An IRQ is generated when the converted voltage is outside the programmed thresholds. The events generated by TIM0, TIM2 and PWM timers can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. GPIOs (General Purpose Input/Output) Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Port 1.15 is an exception, it can be used as general-purpose input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are shared with digital or analog alternate functions. 9/71 Introduction STR750F 1.2 Block Diagram Figure 1. BOOT1, BOOT0 as AF TEST NJTRST JTDI JTCK JTMS JTDO as AF STR750 block diagram ARM7TDMI-S CPU 60MHz AHB JTAG & ICE-RT GP DMA 4 streams AHB BUS MATRIX HRESETN PRESETN SRAM 16KB FLASH 256KB +16KB (RWW) NESTED INTERRUPT CTL CK_RTC CK_SYS HCLK PCLK CLOCK MANAGEMENT VDD_IO VCORE VBACKUP VDDA_PLL VDDA_ADC 32xIRQ 2xFIQ RESET & POWER DC-DC 3.3V TO 1.8V MAIN LOW POWER NRSTIN NRSTOUT VDD_IO V18 V18BKP VSS Arbiter SCLK, MOSI MISO as AF 4 CS as AF SERIAL MEMORY INTERFACE AHB LITE (up to 60MHz) LP OSC OSC 32K FREE OSC PLL OSC 4M XT1 XT2 VDDA_PLL VSSA_PLL RTC_XT1 RTC_XT2 APB BRIDGE CK_USB USB Full Speed 15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC EXT.IT WAKEUP GPIO PORT 0 GPIO PORT 1 GPIO PORT 2 10-bit ADC WATCHDOG RTC USBDP USBDM RX,TX as AF RX,TX,CTS, RTS as AF RX,TX,CTS, RTS as AF RX,TX,CTS, RTS as AF MOSI,MISO, SCK,NSS as AF MOSI,MISO, SCK,NSS as AF SCL,SDA as AF CAN 2.0B FIFO 2x(16x8bit) UART0 FIFO 2x(16x8bit) UART1 FIFO 2x(16x8bit) UART2 FIFO 2x(8x16bit) SSP0 TB TIMER 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF PWM1, PWM1N PWM2, PWM2N PWM3, PWM3N PWM_EMERGENCY as AF TIM0 TIMER TIM1 TIMER I2C TIM2 TIMER PWM TIMER APB (up to 32 MHz) FIFO 2x(8x16bit) SSP1 AF: alternate function on I/O port pin Note: I/Os shown for 100 pin devices. 64-pin devices have the I/O set shown in Figure 3. 10/71 2 Figure 2. STR750F Pin Description ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 TEST VSS_IO ADC_IN6 / UART1_RTS / P0.23 TIM2_OC1/ P2.04 UART1_RTS / P2.03 P2.02 ADC_IN5 / UART1_CTS / P0.22 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / P1.19 JTCK / P1.18 JTDO / P1.17 JTDI / P1.16 NJTRST P2.01 P2.00 UART0_RTS / RTCK / P0.13 SMI_CS1 / ADC_IN2 / UART0_CTS / P0.12 SMI_CS2 / BOOT1 / UART0_TX / P0.11 SMI_CS3 / UART0_RX / P0.10 I2C_SDA / P0.09 I2C_SCL / P0.08 P2.19 P2.18 UART2_RTS / P2.17 ADC_IN12 / UART0_RTS P1.11 ADC_IN7 /UART2_RTS / P0.27 UART2_CTS / P0.26 UART2_TX / P0.25 UART2_RX / P0.24 ADC_IN4 / SSP1_NSS / USB_CK / P0.19 SSP1_MOSI / P0.18 ADC_IN3 / SSP1_MISO / P0.17 SSP1_SCLK / P0.16 P2.16 VDD_IO VDDA_PLL XT2 XT1 VSS_IO VSSA_PLL P2.15 = 16 A/D input channels = 15 External interrupts / Wake-up Lines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 Pinout LQFP100 V18BKP I/Os 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VREG_DIS VSS_IO VSSA_ADC P2.10 P2.11 VDDA_ADC VDD_IO P1.02 / TIM2_OC2 P1.03 / TIM2_TI2 USB_DP USB_DN P0.14 / CAN_RX P0.15 / CAN_TX P2.12 P2.13 P1.15 / WKP_STDBY NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG P2.14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P0.03 / TIM2_TI1 / ADC_IN1 VDD_IO VSS_IO VSS18 V18 P1.00 / TIM0_OC2 P1.01 / TIM0_TI2 P1.13 / ADC_IN14 P1.14/ ADC_IN15 P1.04 / PWM3N / ADC_IN9 P1.05 / PWM3 P1.06 / PWM2N/ ADC_IN10 P1.07 / PWM2 P1.08 / PWM1N/ ADC_IN11 P2.05 / PWM3N P2.06 / PWM3 P2.07 / PWM2N P2.08 / PWM2 P2.09 / PWM1N P1.09 / PWM1 P1.10 / PWM_EMERGENCY P0.04 / SMI_CS0 / SSP0_NSS P0.05 / SSP0_SCLK / SMI_CK P0.06 / SMI_DIN / SSP0_MISO P0.07 / SMI_DOUT / SSP0_MOSI Pin Description 11/71 Pin Description Figure 3. LQFP64 Pinout STR750F ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1 / P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 TEST VSS_IO_4 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / P1.19 JTCK / P1.18 JTDO / P1.17 JTDI / P1.16 NJTRST UART0_RTS / RTCK / P0.13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 V18BKP I/Os 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.09 / PWM1 P1.10 / PWM_EMERGENCY P0.04 / SMI_CS0 /SSP0_NSS P0.05 / SSP0_SCLK / SMI_CK P0.06 / SMI_DIN / SSP0_MISO P0.07 / SMI_DOUT / SSP0_MOSI VREG_DIS VSS_IO_2 VSSA_ADC VDDA_ADC VDD_IO_2 P1.03 / TIM2_TI2 P0.14 / CAN_RX or USB_DP P0.15 / CAN_TX or USB_DN NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG P0.03 / TIM2_TI1 / ADC_IN1 VDD_IO_1 VSS_IO_1 VSS18 V18 P1.04 / PWM3N / ADC_IN9 P1.05 / PWM3 P1.06 / PWM2N / ADC_IN10 P1.07 / PWM2 = 11 A/D input channels = 13 External interrupts / Wake-up Lines 12/71 SMI_CS1 / ADC_IN2 / UART0_CTS / P0.12 SMI_CS2 / BOOT1 / UART0_TX / P0.11 SMI_CS3 / UART0_RX / P0.10 I2C_SDA/ P0.09 I2C_SCL / P0.08 ADC_IN12 / UART0_RTS / P1.11 ADC_IN4 / SSP1_NSS / USB_CK / P0.19 SSP1_MOSI / P0.18 ADC_IN3 / SSP1_MISO / P0.17 SSP1_SCLK / P0.16 VDD_IO_3 VDDA_PLL XT2 XT1 VSS_IO_3 VSSA_PLL P1.08 / PWM1N / ADC_IN11 STR750F Table 3. 1 A B C D E F G H J K P0.03 P1.12 P0.31 P0.29 P0.28 P2.03 Pin Description LFBGA100 ball connections 2 3 4 P1.04 P1.05 V18 VSS18 5 6 7 P0.05 P0.04 VSS_IO VDD_IO 8 P0.06 P2.13 VSSA_ADC VDDA_ADC 9 P0.07 P1.03 P2.11 P2.12 10 P1.02 P2.10 USB_DP USB_DN P0.14 P0.15 XRTC2 XRTC1 VSS_IO P1.13 P1.14 P0.02 P0.01 P0.00 VDD_IO P0.30 VSS_IO P0.23 P0.22 P0.21 P0.20 P1.06 P1.08 P1.07 P1.09 P1.10 P2.09 P1.01 P1.15 VSS_IO TEST P1.00 NRSTOUT VREG_DIS NRSTIN P2.02 P2.01 P2.19 P0.27 P0.18 P2.04 P2.05 P2.00 P2.07 P2.18 P2.17 P0.19 P0.26 P0.17 P0.16 P2.06 2.08 P0.24 P0.25 XT1 VSS18 V18REG P2.14 P2.15 XT2 VSSBKP V18BKP P2.16 VDD_IO NJTRST P1.18 P1.19 P0.13 P0.11 P0.10 P1.16 P1.17 P0.12 P1.11 P0.09 P0.08 VDDA_PLL VSSA_PLL Table 4. LFBGA64 ball connections 1 2 VSS_IO VDD_IO P0.02 P0.28 P1.19 NJTRST P0.12 P0.09 3 P1.04 P1.05 P0.00 TEST P0.20 P1.16 P1.11 P0.08 4 P1.06 P1.07 V18 VSS_IO P0.21 P1.17 P0.19 P0.17 5 P1.08 P1.09 VSS18 6 P0.05 P0.04 VDD_IO 7 P0.06 P1.10 VSS_IO 8 P0.07 P1.03 P0.14 P0.15 XRTC2 XRTC1 A B C D E F G H P0.03 P1.12 P0.01 P0.29 P1.18 P0.13 P0.11 P0.10 VREG_DIS VDDA_ADC VSSA_ADC NRSTOUT V18REG VDD_IO P0.18 NRSTIN VSS18 VSS_IO P0.16 V18BKP VSSBKP VDDA_PLL VSSA_PLL XT2 XT1 13/71 Pin Description STR750F 2.0.1 Pin Description Table Legend / Abbreviations for Table 5: Type: Input Levels: I = input, O = output, S = supply, All Inputs are LVTTL at VDD_IO = 3.3V+/-0.3V or TTL at VDD_IO = 5V 0.5V. In both cases, TT means VILmax =0.8V VIHmin=2.0V All inputs can be configured as floating or with internal weak pull-up or pull down (pu/pd) All Outputs can be configured as Open Drain (OD) or Push-Pull (PP) (see also note 6 below Table 5). There are 3 different types of Output with different drives and speed characteristics: - O8: fmax = 40 MHz on CL=50pF and 8 mA static drive capability for VOL=0.4V and up to 20 mA for VOL=1.3V (seeOutput driving current on page 54) - O4: fmax = 20 MHz on CL=50pF and 4 mA static drive capability for VOL=0.4V (seeOutput driving current on page 54) - O2: fmax = 10 MHz on CL=50pF and 2 mA static drive capability of for VOL=0.4V (seeOutput driving current on page 54) Inputs: Outputs: External Interrupts/wake-up lines: EITx 14/71 STR750F Pin Description Port Reset State The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13 which are configured as JTAG alternate functions: The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready to accept JTAG sequences. The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is configured in output push-pull only when serial JTAG data must be output. The JTAG output RTCK is always configured as output push-pull. It outputs '0' level during the reset phase and then outputs the JTCK input signal resynchronized 3 times by the internal AHB clock. The GPIO_PCx registers do not control JTAG AF selection, so the reset values of GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO section of the STR750 Reference Manual for the register description and reset values. P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first word of user code at address 0000 0000h. When booting from SMI (and only in this case), the reset state of the following GPIOs is "SMI alternate function output enabled": - - - - P0.07 (SMI_DOUT) P0.05 (SMI_CLK) P0.04 (SMI_CS0) P0.06 (SMI_DIN) Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected. To avoid excess power consumption, unused I/O ports must be tied to ground. Table 5. Pin n Input Level STR750F pin description Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 1 B1 1 B1 P1.12 / ADC_IN13 I/O TT X X EIT12 O8 X X Port 1.12 ADC: Analog input 13 TIM2: Output Compare 1(2) ADC: Analog input 0 2 B2 2 P0.02 / C2 TIM2_OC1 / ADC_IN0 C1 P0.01 / TIM0_TI1 / MCO I/O TT X X EIT0 O8 X X Port 0.02 3 B3 3 I/O TT X X O8 X X Port 0.01 Port 0.00 / Boot mode selection input 0 Port 0.31 Port 0.30 TIM0: Input Main Clock Capture / trigger Output / external clock 1 4 C2 4 P0.00 / C3 TIM0_OC1 / BOOT0 P0.31 / TIM1_TI2 P0.30 / TIM1_OC2 I/O TT X X O8 X X TIM0: Output Compare 1 5 6 C1 D2 I/O I/O TT TT X X X X O2 O2 X X X X TIM1: Input Capture / trigger / external clock 2 TIM1: Output Compare 2 15/71 Pin Description Table 5. Pin n Input Level STR750F STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 7 8 9 10 11 D1 E1 E5 E4 E2 5 6 7 8 D1 D2 P0.29 / TIM1_TI1 / ADC_IN8 P0.28 / TIM1_OC1 I/O I/O I S I/O TT TT X X X X O2 O2 X X X X Port 0.29 Port 0.28 TIM1: Input Capture 1 ADC: Analog input 8 TIM1: Output Compare 1 D3 TEST D4 VSS_IO P0.23 / UART1_RTS / ADC_IN6 P2.04 / TIM2_OC1 P2.03 / UART1_RTS P2.02 P0.22 / UART1_CTS / ADC_IN5 Reserved, must be tied to ground Ground Voltage for digital I/Os TT X X O2 X X Port 0.23 UART1: Ready To Send output(2) TIM2: Output Compare 1(2) UART1: Ready To Send output(2) ADC analog input 6 12 F5 I/O TT X X O2 X X Port 2.04 13 14 15 F1 F4 E3 I/O I/O I/O TT TT TT X X X X X X O2 O2 O2 X X X X X X Port 2.03 Port 2.02 Port 0.22 UART1: Clear To Send input ADC: Analog input 5 16 17 F2 F3 9 10 E4 E3 P0.21 / UART1_TX P0.20 / UART1_RX P1.19 / JTMS I/O I/O TT TT X X X X O2 O2 X X X X Port 0.21 Port 0.20 JTAG mode selection input(4) JTAG clock input(4) JTAG data output(4) JTAG data input(4) UART1: Transmit data output (remappable to P0.15)(2) UART1: Receive data input (remappable to P0.14)(2) Port 1.19 18 G3 11 E2 I/O TT X X O2 X X 19 20 21 22 23 24 G2 H3 H2 G1 G4 G5 12 13 14 15 E1 P1.18 / JTCK F4 P1.17 / JTDO F3 P1.16 / JTDI F2 NJTRST P2.01 P2.00 P0.13 / RTCK / UART0_RTS I/O I/O I/O I I/O I/O TT TT TT TT TT TT X X X X X X O2 O8 O2 X X X X X X Port 1.18 Port 1.17 Port 1.16 JTAG reset input(3) X X X X O2 O2 X X X X Port 2.01 Port 2.00 JTAG return clock output(4) Port 0.13 UART0: Ready To Send output(2) UART0: Clear To Send input ADC: Analog input 2 25 H1 16 F1 I/O TT X X O8 X X 26 J2 17 G2 P0.12 / UART0_CTS / ADC_IN2 / SMI_CS1 I/O TT X X O4 X X Port 0.12 Serial Memory Interface: chip select output 1 16/71 STR750F Table 5. Pin n Input Level Pin Description STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 27 J1 P0.11 / UART0_TX / 18 G1 BOOT1 / SMI_CS2 P0.10 / 19 H1 UART0_RX / SMI_CS3 20 H2 P0.09 / I2C_SDA 21 H3 P0.08 / I2C_SCL P2.19 P2.18 P2.17 / UART2_RTS P1.11 22 G3 /UART0_RTS ADC_IN12 P0.27 / UART2_RTS / ADC_IN7 P0.26 / UART2_CTS P0.25 / UART2_TX P0.24 / UART2_RX I/O TT X X O4 X X Port 0.11/Boot mode selection input 1 Port 0.10 Port 0.09 Port 0.08 Port 2.19 Port 2.18 Port 2.17 UART0: Transmit data output Serial Memory Interface: chip select output 2 Serial Memory Interface: chip select output 3 28 29 30 31 32 33 K1 K2 K3 H4 H5 H6 I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT X X X X X X X X X X X X EIT4 O2 O4 X X X X X X X X X X X X UART0: Receive Data input I2C: Serial Data I2C: Serial clock EIT3 O4 O2 O2 O2 UART2: Ready To Send output(2) UART0: Ready To Send output(2) UART2: Ready To Send output(6) ADC: Analog input 12 ADC: Analog input 7 34 J3 I/O TT X X EIT11 O8 X X Port 1.11 35 J4 I/O TT X X O2 X X Port 0.27 36 37 38 J6 J7 H7 I/O I/O I/O TT TT TT X X X X X X O2 O2 O2 X X X X X X Port 0.26 Port 0.25 Port 0.24 UART2: Clear To Send input UART2: Transmit data output (remappable to P0.13)(6) UART2: Receive data input (remappable to P0.12)(6) SSP1: Slave select input (remappable to P0.11)(6) USB: 48 MHz Clock input ADC: Analog input 4 39 J5 P0.19 / USB_CK / 23 G4 SSP1_NSS / ADC_IN4 I/O TT X X EIT6 O2 X X Port 0.19 40 K4 24 H5 P0.18 / SSP1_MOSI I/O TT X X O2 X X Port 0.18 SSP1: Master out/slave in data (remappable to P0.10)(6) SSP1: Master in/slave out data (remappable to P0.09)(6) ADC: Analog input 3 41 K5 P0.17 / 25 H4 SSP1_MISO / ADC_IN3 26 H6 P0.16 / SSP1_SCLK P2.16 27 G5 VDD_IO 28 G7 VDDA_PLL I/O TT X X O2 X X Port 0.17 42 43 44 45 K6 H9 J9 K9 I/O I/O S S TT TT X X X X O2 O2 X X X X Port 0.16 Port 2.16 SSP1: serial clock (remappable to P0.08)(6) Supply voltage for digital I/Os Supply voltage for PLL 17/71 Pin Description Table 5. Pin n Input Level STR750F STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 46 47 48 49 50 51 K8 K7 J10 K10 J8 H8 29 H7 XT2 4 MHz main oscillator 30 H8 XT1 31 G6 VSS_IO 32 G8 VSSA_PLL P2.15 P2.14 S S I/O I/O TT TT X X X X O2 O2 X X X X Ground voltage for digital I/Os Ground voltage for PLL Port 2.15 Port 2.14 Stabilization for main voltage regulator. Requires external capacitors of at least 10F between V18REG and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used, 52 G8 33 F5 V18REG S 53 54 F8 F9 34 35 F6 VSS18 F7 VSSBKP S S Ground Voltage for the main voltage regulator Stabilization for low power voltage regulator. Ground Voltage for the low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and VSSBKP. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used, X 32 kHz oscillator for Realtime Clock X 55 G9 36 E7 V18BKP S 56 57 58 59 60 61 62 63 64 65 66 H10 37 F8 XRTC1 E8 XRTC2 E5 NRSTOUT E6 NRSTIN P1.15 / WKP_STDBY P2.13 P2.12 O I I I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT X X X X X X X X X EIT5 EIT15 O2 O2 O2 O2 X X X X X X X X G10 38 E7 E9 D6 B8 D9 F10 E10 D10 C10 39 40 X X X Reset output Reset input Port 1.15 Port 2.13 Port 2.12 Port 0.15 Port 0.14 CAN: Transmit data output CAN: Receive data input Wake-up from STANDBY input pin 41 D8 (5) (5) P0.15 / CAN_TX P0.14 / CAN_RX USB_DN USB_DP 42 C8 (5) (5) 41 D8 (5) (5) USB: bidirectional data (data -) USB: bidirectional data (data +) TIM2: Input Capture / trigger / external clock 2 (remappable to P0.07)(6) TIM2: Output compare 2 (remappable to P0.06)(6) 42 C8 (5) (5) 67 B9 43 B8 P1.03 / TIM2_TI2 P1.02 / TIM2_OC2 I/O TT X X O2 X X Port 1.03 68 69 70 A10 D7 D8 I/O S S TT X X O2 X X Port 1.02 44 C6 VDD_IO 45 D6 VDDA_ADC Supply Voltage for digital I/Os Supply Voltage for A/D converter 18/71 STR750F Table 5. Pin n Input Level Pin Description STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 71 72 73 74 75 76 C9 B10 C8 C7 E8 A9 P2.11 P2.10 46 D7 VSSA_ADC 47 C7 VSS_IO 48 D5 VREG_DIS 49 P0.07 / A8 SMI_DOUT / SSP0_MOSI A7 P0.06 / SMI_DIN / SSP0_MISO I/O I/O S S I I/O TT TT X X X X O2 O2 X X X X Port 2.11 Port 2.10 Ground Voltage for A/D converter Ground Voltage for digital I/Os TT TT X X EIT2 O4 X X Voltage Regulator Disable input Port 0.07 Serial Memory Interface: data output Serial Memory Interface: data input SSP0: Serial clock Serial Memory Interface: chip select output 0 SSP0: Master out Slave in data SSP0: Master in Slave out data Serial Memory Interface: Serial clock output SSP0: Slave select input 77 A8 50 I/O TT X X O4 X X Port 0.06 78 A7 51 P0.05 / A6 SSP0_SCLK / SMI_CK B6 P0.04 / SMI_CS0 / SSP0_NSS I/O TT X X EIT1 O4 X X Port 0.05 79 B7 52 I/O TT X X O4 X X Port 0.04 80 81 82 83 84 85 86 C5 B6 C6 G7 G6 F7 F6 53 54 P1.10 B7 PWM_EMERGE NCY B5 P1.09 / PWM1 P2.09 / PWM1N P2.08 / PWM2 P2.07 / PWM2N P2.06 / PWM3 P2.05 / PWM3N P1.08 / PWM1N / ADC_IN11 I/O I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT TT X X X X X X X X X X X X X X EIT10 EIT9 O2 O4 O2 O2 O2 O2 O2 X X X X X X X X X X X X X X Port 1.10 Port 1.09 Port 2.09 Port 2.08 Port 2.07 Port 2.06 Port 2.05 PWM: Emergency input PWM: PWM1 output PWM: PWM1 complementary output(2) PWM: PWM2 output(2) PWM: PWM2 complementary output(2) PWM: PWM3 output(2) PWM: PWM3 complementary output(2) PWM: PWM1 complementary output(6) ADC: analog input 11 87 88 89 90 91 A6 B5 A5 B4 A4 55 56 57 58 59 A5 I/O I/O I/O I/O I/O TT TT TT TT TT X X X X X X X X X X EIT7 EIT8 O4 O4 O4 O4 O4 X X X X X X X X X X Port 1.08 Port 1.07 Port 1.06 Port 1.05 Port 1.04 B4 P1.07 / PWM2 A4 P1.06 / PWM2N / ADC_IN10 PWM: PWM2 output(2) PWM: PWM2 complementary output(2) ADC: analog input 10 B3 P1.05 / PWM3 A3 P1.04 / PWM3N / ADC_IN9 P1.14 / ADC_IN15 P1.13 / ADC_IN14 PWM: PWM3 output(2) PWM: PWM3 complementary output(2) ADC: analog input 9 92 93 A3 A2 I/O I/O TT TT X X X X EIT13 O8 O8 X X X X Port 1.14 Port 1.13 ADC: analog input 15 ADC: analog input 14 19/71 Pin Description Table 5. Pin n Input Level STR750F STR750F pin description (continued) Usable in Standby Input Ext. int /Wake-up Output LFBGA100 LQPFP100 pu/pd Pin Name Capability LFBGA64 LQPFP64 floating OD (1) PP Main function (after reset) Type Alternate function 94 D5 P1.01 / TIM0_TI2 P1.00 / TIM0_OC2 I/O TT X X O2 X X Port 1.01 TIM0: Input Capture / trigger / external clock 2 (remappable to P0.05)(6) TIM0: Output compare 2 (remappable to P0.04)(6) 95 E6 I/O TT X X O2 X X Port 1.00 96 C4 60 C4 V18 S Stabilization for main voltage regulator. Requires external capacitors 33nF between V18 and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used. Ground Voltage for the main voltage regulator. Ground Voltage for digital I/Os Supply Voltage for digital I/Os TT X X O2 X X Port 0.03 TIM2: Input Capture / trigger / external clock 1 ADC: analog input 1 97 98 99 100 D4 D3 C3 A1 61 C5 VSS18 62 63 64 A2 VSS_IO B2 VDD_IO A1 P0.03 / TIM2_TI1 / ADC_IN1 S S S I/O 1. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O pin and VDD_IO. 2. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where these functions are listed in the table. 3. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to NRSTOUT pin (if available) or NRSTIN. 4. After reset, these pins are enabled as JTAG alternate function see (Port Reset State on page 15). To use these ports as general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case, debugging these I/Os via JTAG is not possible). 5. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while for the second one, they are mapped to P0.15/CAN_TX and P0.14/RX. 6. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description. 20/71 STR750F Figure 4. Required external capacitors when regulators are used 33 nF 33 nF 96 VSS18 V18 97 V18BKP 55 VSSBKP 54 1F Pin Description 61 60 VSS18 V18 V18BKP 36 VSSBKP 35 1F LQFP100 VSS18 53 10 F LQFP64 VSS18 V18REG 52 VDD_IO 44 1 F 33 nF 34 10 F V18REG 33 VDD_IO 27 1 F 33 nF D4 C4 VSS18 V18 V18BKP G9 VSSBKP F9 1F C5 C4 VSS18 V18 V18BKP E7 VSSBKP F7 1F LFBGA100 LFBGA64 VSS18 F8 10 F V18REG G8 VSS18 F6 10 F V18REG F5 VDD_IO G5 1 F VDD_IO J9 1 F 21/71 Pin Description STR750F 2.1 Memory map Figure 5. Memory map Peripheral Memory Space 32 Kbytes 0xFFFF FFFF 0xFFFF FC00 0xFFFF FBFF 0xFFFF F800 0xFFFF F7FF 0xFFFF F400 0xFFFF F3FF 0xE000 0000 0xDFFF FFFF Addressable Memory Space 4 Gbytes 0xFFFF FFFF 0xFFFF 8000 APB TO ARM7 BRIDGE 32K Reserved EIC EXTIT 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 7 FLASH Memory Space 128/256 Kbytes 0x2010 DFFF 0x2010 C000 0x2010 0017 0x2010 0000 0xFFFF F000 0xFFFF EFFF 0xFFFF EC00 0xFFFF EBFF RTC DMA Reserved 6 0xC000 0000 0xBFFF FFFF SystemMemory 8K Flash registers 0xFFFF E800 0xFFFF E7FF 24B GPIO I/O Ports 0xFFFF E400 0xFFFF E3FF 0xFFFF E000 0xFFFF DFFF 0xFFFF DC00 0xFFFF DBFF Reserved UART2 UART1 UART0 Reserved I2C Reserved CAN Reserved SSP1 SSP0 Reserved WDG Reserved USB Registers Reserved 5 0xA000 0000 0x9FFF FFFF 0xFFFF D800 0xFFFF D7FF 0x200C 0x200C 0x200C 0x200C 0x200C 4000 3FFF 2000 1FFF 0000 0xFFFF D400 0xFFFF D3FF B1F1 B1F0 8K 8K 0xFFFF D000 0xFFFF CFFF 0xFFFF CC00 0xFFFF CBFF 0xFFFF C800 0xFFFF C7FF 0xFFFF C400 0xFFFF C3FF 4 0x9000 0013 0x9000 0000 0x83FF FFFF 0x8000 0000 0x7FFF FFFF SMI Registers 20B 4 x 16M SMI Ext. Memory 0xFFFF C000 0xFFFF BFFF 0xFFFF BC00 0xFFFF BBFF 3 0x6000 0047 0x6000 0000 0x5FFF FFFF CONF + MRCC 0xFFFF B800 0xFFFF B7FF 0xFFFF B400 0xFFFF B3FF 1K 0x2003 FFFF 0xFFFF B000 0xFFFF AFFF B0F7(2) 64K 0xFFFF AC00 0xFFFF ABFF 0xFFFF A800 0xFFFF A7FF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 2 0x4000 3FFF 0x4000 0000 0x3FFF FFFF Internal SRAM 0x2003 0000 0x2002 FFFF 16K 0x2002 0000 0x2001 FFFF B0F6(2) 64K A400 A3FF A200 USB RAM 256 x16-bit A000 9FFF Reserved 0xFFFF 9C00 0xFFFF 9BFF PWM 1 0x2010 0017 0x2000 0000 0x1FFF FFFF Internal Flash B0F5 64K 0xFFFF 9800 0xFFFF 97FF 0xFFFF 9400 0xFFFF 93FF TIM2 TIM1 128K/256K+16K+32B 0x2001 0000 0x2000 FFFF 0xFFFF 9000 0xFFFF 8FFF B0F4 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 8000 7FFF 6000 5FFF 4000 3FFF 2000 1FFF 0000 32K 8K 8K 8K 8K TIM0 TB Timer ADC Reserved 0xFFFF 8C00 0xFFFF 8BFF 0xFFFF 8800 0xFFFF 87FF 0xFFFF 8400 0xFFFF 83FF 0xFFFF 8000 0 0x0000 0000 Boot Memory(1) B0F3 B0F2 B0F1 B0F0 128K/256K (1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h (2) Only available in STR750Fx2 Reserved 22/71 STR750F Electrical parameters 3 3.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 3.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25 C and TA=TAmax (given by the selected temperature range). Data based on product characterisation, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 3.1.2 Typical values Unless otherwise specified, typical data are based on TA=25 C, VDD_IO=3.3 V (for the 3.0 VVDD_IO3.6 V voltage range) and V18=1.8 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 3.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 23/71 Electrical parameters STR750F 3.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Figure 6. Pin loading conditions STR7 PIN CL=50pF 3.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 7. Pin input voltage STR7 PIN VIN 24/71 STR750F Electrical parameters 3.1.6 Power Supply Schemes When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below. Power supply scheme 1: Single external 3.3 V power source Figure 8. Power supply scheme 1 V18_BKP 1F VSS_BKP IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON NORMAL MODE VBACKUP VREG_DIS V18 33nF LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18 BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) VSS18 V18REG 10F VSS18 VDD_IO 3.3V +/-0.3V 1F VSS_IO MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=3.3V OUT VCORE KERNEL LOGIC (CPU & DIGITAL & MEMORIES) GP I/Os IN I/O LOGIC VDD_PLL VSS_PLL 3.3V PLL VDD_ADC 3.3V VSS_ADC ADCIN ADC 25/71 Electrical parameters STR750F Power supply scheme 2: Dual external 1.8V and 3.3V supply Figure 9. Power supply scheme 2 V18_BKP VSS_BKP VDD_IO VREG_DIS OFF VBACKUP VLPVREG V18 V18REG 1.8V VSS18 VDD_IO 3.3V +/-0.3V LOW POWER VOLTAGE REGULATOR BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) POWER SWITCH OFF MAIN VOLTAGE REGULATOR VSS_IO VMVREG VCORE KERNEL (CORE & DIGITAL & MEMORIES) VIO=3.3V OUT GP I/Os I/O LOGIC IN VDD_PLL VSS_PLL 3.3V PLL VDD_ADC 3.3V VSS_ADC ADCIN ADC NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON 26/71 STR750F Electrical parameters Power supply scheme 3: Single external 5 V power source Figure 10. Power supply scheme 3 V18_BKP 1F VSS_BKP IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON NORMAL MODE VBACKUP VREG_DIS V18 33nF LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18 BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) VSS18 V18REG 10F VSS18 VDD_IO 5.0V +/-0.5V 1F VSS_IO MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=5.0V OUT VCORE KERNEL LOGIC (CPU & DIGITAL & MEMORIES) GP I/Os IN I/O LOGIC VDD_PLL VSS_PLL 5.0V PLL VDD_ADC 5.0V VSS_ADC ADCIN ADC 27/71 Electrical parameters STR750F Power supply scheme 4: Dual external 1.8 V and 5.0 V supply Figure 11. Power supply scheme 4 V18_BKP VSS_BKP VDD_IO VREG_DIS OFF VBACKUP VLPVREG V18 V18REG 1.8V VSS18 VDD_IO 5.0V +/-0.5V LOW POWER VOLTAGE REGULATOR BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) POWER SWITCH OFF MAIN VOLTAGE REGULATOR VSS_IO VMVREG VCORE KERNEL (CORE & DIGITAL & MEMORIES) VIO=5.0V OUT GP I/Os I/O LOGIC IN VDD_PLL VSS_PLL 5.0V PLL VDD_ADC 5.0V VSS_ADC ADCIN ADC NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON 3.1.7 I/O characteristics versus the various power schemes (3.3V or 5.0V) Unless otherwise mentioned, all the I/O characteristics are valid for both VDD_IO=3.0 V to 3.6 V with bit EN33=1 VDD_IO=4.5 V to 5.5 V with bit EN33=0 When VDD_IO=3.0 V to 3.6 V, I/Os are not 5V tolerant. 3.1.8 Current Consumption Measurements All the current consumption measurements mentioned below refer to Power scheme 1 and 2 as described in Figure 12 and Figure 13 28/71 STR750F Electrical parameters Figure 12. Power consumption measurements in power scheme 1 (regulators enabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator I33 transistor V18 pins (including V18BKP) I18 1.8V internal load 3.3V internal load IDDA_ADC PLL load ADC load IDD 3.3V Supply IDD is measured, which corresponds to the total current consumption : IDD = IDDA_PLL + IDDA_ADC + I33 + I18 Figure 13. Power consumption measurements in power scheme 2 (regulators disabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 3.3V internal load IDDA_ADC PLL load ADC load IDD_v33 3.3V Supply 1.8V Supply IDD_v18 V18 pins (including V18BKP) I33 I18 IDD_v33 and IDD_v18 are measured which correspond to: IDD_v33 = IDDA_PLL + IDDA_ADC + I33 IDD_v18 = I18 1.8V internal load 29/71 Electrical parameters STR750F Figure 14. Power consumption measurements in power scheme 3 (regulators enabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator I50 transistor V18 pins (including V18BKP) I18 1.8V internal load 5.0V internal load IDDA_ADC PLL load ADC load IDD 5.0V Supply IDD is measured, which corresponds to the total current consumption : IDD = IDDA_PLL + IDDA_ADC + I50 + I18 Figure 15. Power consumption measurements in power scheme 4 (regulators disabled) VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 5.0V internal load IDDA_ADC PLL load ADC load IDD_v50 5.0V Supply 1.8V Supply IDD_v18 V18 pins (including V18BKP) I50 I18 IDD_v50 and IDD_v18 are measured which correspond to: IDD_v50= IDDA_PLL + IDDA_ADC + I50 IDD_v18 = I18 1.8V internal load 30/71 STR750F Electrical parameters 3.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 3.2.1 Voltage characteristics Table 6. Symbol Voltage characteristics Ratings Min -0.3 -0.3 VSS-0.3 to VDD_IO+0.3 Max 6.5 2.0 VSS-0.3 to VDD_IO+0.3 50 25 50 see : Absolute Maximum Ratings (Electrical Sensitivity) on page 51 see : Absolute Maximum Ratings (Electrical Sensitivity) on page 51 mV Unit V VDD_x - VSS_X(1) Including VDDA_ADC and VDDA_PLL V18 - VSS18 Digital 1.8 V Supply voltage on all V18 power pins (when 1.8 V is provided externally) Input voltage on any pin (2) Variations between different 3.3 V or 5.0 V power pins Variations between different 1.8 V power pins(3) Variations between all the different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) VIN |VDDx| |V18x| |VSSX - VSS| VESD(HBM) VESD(MM) 1. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always be connected to the external 3.3V or 5.0V supply. When powered by 3.3V, I/Os are not 5V tolerant. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Electrical parameters STR750F 3.2.2 Current characteristics Table 7. Symbol IVDD_IO(1) IVSS_IO(1) IIO Current characteristics Ratings Total current into VDD_IO power lines (source) (2) Total current out of VSS ground lines (sink) (2) Maximum value 150 150 25 - 25 Unit Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRSTIN pin IINJ(PIN) (3) & (4) IINJ(PIN)(3) Injected current on XT1 and XT2 pins Injected current on any other pin (5) pins) (5) mA 5 5 5 25 Total injected current (sum of all I/O and control 1. The user can use GPIOs to source or sink high current (up to 20 mA for O8 type High Sink I/Os). In this case, the user must ensure that these absolute max. values are not exceeded (taking into account the RUN power consumption) and must follow the rules described in Section 3.3.8: I/O port pin characteristics on page 53. 2. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always be connected to the external 3.3V or 5.0V supply. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Thermal characteristics Table 8. Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Value -65 to +150 Unit C Maximum junction temperature (see Section 4.2: Thermal characteristics on page 70) 32/71 STR750F Electrical parameters 3.3 3.3.1 Operating conditions General operating conditions Subject to general operating conditions for VDD_IO, and TA unless otherwise specified. Table 9. Symbol General operating conditions Parameter Conditions Accessing SRAM with 0 wait states Accessing Flash in burst mode, TA85 C Min 0 0 Max 64 60 56 0 0 0 3.0 4.5 1.65 6 Suffix Version -40 -40 32 16 32 3.6 5.5 1.95 85 105 C C V MHz MHz Unit fHCLK Internal AHB Clock frequency Accessing Flash in burst mode TA>85 C Accessing Flash with 0 wait states Accessing Flash in RWW mode fPCLK Internal APB Clock frequency Standard Operating Voltage Power Scheme 1 & 2 VDD_IO Standard Operating Voltage Power Scheme 3 & 4 Standard Operating Voltage Power Scheme 2 & 4 Ambient temperature range 7 Suffix Version V18 TA 3.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Symbol tVDD_IO Operating conditions at power-up / power-down Parameter VDD_IO rise time rate V18 rise time rate (1) When 1.8 V power is supplied externally 20 20 Conditions Min(1) 20 20 Typ Max(1) Unit s/V ms/V s/V ms/V tV18 1. Data guaranteed by characterization, not tested in production. 33/71 Electrical parameters STR750F 3.3.3 Embedded voltage regulators Subject to general operating conditions for VDD_IO, and TA Table 11. Symbol VMVREG VLPVREG Embedded voltage regulators Parameter MVREG power supply(1) LPVREG power supply(2) Voltage Regulators start-up time (to reach 90% of final V18 value) at VDD_IO power-up(3) Conditions load <150 mA load <10 mA VDD_IO rise slope = 20 s/V VDD_IO rise slope = 20 ms/V Min 1.65 1.30 Typ 1.80 1.40 80 35 Max 1.95 1.50 Unit V V s ms tVREG_PWRUP(1) 1. VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case: - In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2. - In STANDBY mode. See note 2. 2. In STANDBY mode, VLPVREG is observed on the V18BKP pin In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins. 3. Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET during this start-up time. 34/71 STR750F Electrical parameters 3.3.4 Supply current characteristics The current consumption is measured as described in Figure 12 on page 29 and Figure 13 on page 29. Subject to general operating conditions for VDD_IO, and TA Maximum power consumption For the measurements in Table 12 and Table 13, the MCU is placed under the following conditions: All I/O pins are configured in output push-pull 0 All peripherals are disabled except if explicitly mentioned. Embedded Regulators are used to provide 1.8 V (except if explicitly mentioned). Maximum power consumption in RUN and WFI modes Parameter Conditions (1) Typ(2) Max (3) Unit Table 12. Symbol IDD External Clock with PLL multiplication, code running from RAM, all peripherals enabled in the 3.3V Supply current in MRCC_PLCKEN register: fHCLK=60 and 5V RUN mode MHz, fPCLK=30 MHz range Single supply scheme see Figure 12 / Figure 14 External Clock, code running from RAM: fHCLK=60 MHz, fPCLK=30 MHz 3.3V Supply current in Single supply scheme see and 5V WFI mode Figure 12./ Figure 14 range Parameter setting BURST=1, WFI_FLASHEN=1 80 90 mA 62 67 mA 1. The conditions for these consumption measurements are described at the beginning of Section 3.3.4. 2. Typical data are based on TA=25C, VDD_IO=3.3V or 5.0V and V18=1.8V unless otherwise specified. 3. Data based on product characterisation, tested in production at VDD_IO max and V18 max (1.95V in dual supply mode or regulator output value in single supply mode) and TA max. 35/71 Electrical parameters Table 13. Symbol STR750F Maximum power consumption in STOP and STANDBY modes Max(3) Parameter Conditions (1) Typ(2) TA 25C 16 8 3 22 8 5 20 25 TA 85C 117 60 TBD 160 60 TBD 25 30 TA 105C 250 110 TBD 310 110 TBD 28 33 A Unit LP_PARAM bits: ALL OFF(4) Single supply scheme see Figure 12. Supply current in STOP mode IDD LP_PARAM bits: ALL OFF Dual supply scheme see Figure 13. LP_PARAM bits: ALL OFF(4) Single supply scheme see Figure 10 LP_PARAM bits: ALL OFF Dual supply scheme see Figure 11 Supply current in STANDBY mode 3.3V range IDD_V18 IDD_V33 5V range IDD_V18 IDD_V50 3.3 V range 12 5 <1 15 5 3 10 15 A A A RTC OFF 5V range 1. The conditions for these consumption measurements are described at the beginning of Section 3.3.4. 2. Typical data are based on TA=25C, VDD_IO=3.3V or 5.0V and V18=1.8V unless otherwise specified. 3. Data based on product characterisation, tested in production at VDD_IO max and V18 max (1.95V in dual supply mode or regulator output value in single supply mode). 4. In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4V, which significantly reduces the leakage currents. 36/71 STR750F Electrical parameters Figure 16. Power consumption in STOP mode Figure 17. Power consumption in STOP mode in Single supply scheme (3.3 V Single supply scheme (5 V range) range) 300 250 IStop (uA) 200 150 100 50 0 -40 25 45 55 Temp (C) 75 95 105 TYP (3.3V) IStop (uA) MAX (3.6V) 250 200 150 100 50 0 -40 25 45 55 Temp (C) 75 95 105 TYP (5.0V) MAX (5.5V) 350 300 Figure 18. Power consumption in STANDBY mode (3.3 V range) Figure 19. Power consumption in STANDBY mode (5 V range) 30 25 IStandby (uA) 20 15 10 5 0 -40 25 Temp (C) 105 TYP (3.3V) IStandby (uA) MAX (3.6V) 35 30 25 20 15 10 5 0 -40 25 Temp (C) 105 TYP (5.0V) MAX (5.5V) 37/71 Electrical parameters STR750F Typical power consumption The following measurement conditions apply to Table 14, Table 15 and Table 16. In RUN mode: Program is executed from Flash (except if especially mentioned). The program consists of an infinite loop. When fHCLK > 32 MHz, burst mode is activated. A standard 4 MHz crystal source is used. In all cases the PLL is used to multiply the frequency. All measurements are done in the single supply scheme with internal regulators used (see Figure 12) In WFI Mode the measurement conditions are similar to RUN mode (OSC4M and PLL enabled). In addition, the Flash can be disabled depending on burst mode activation: - For AHB frequencies greater than 32 MHz, burst mode is activated and the Flash is kept enabled by setting the WFI_FLASH_EN bit (this bit cannot be reset when burst mode is activated). For AHB frequencies less than or equal to 32 MHz, burst mode is deactivated, WFI_FLASH_EN is reset and the LP_PARAM14 bit is set (Flash is disabled in WFI mode). In WFI Mode: - In SLOW mode: The same program as in RUN mode is executed from Flash. The CPU is clocked by the FREEOSC, OSC4M, LPOSC or OSC32K. Only EXTIT peripheral is enabled in the MRCC_PCLKEN register. In SLOW-WFI, the measurement conditions are similar to SLOW mode (CPU clocked by a low frequency clock). In addition, the LP_PARAM14 bit is set (FLASH is OFF). The WFI routine itself is executed from SRAM (it is not allowed to execute a WFI from the internal FLASH) Several measurements are given: in the single supply scheme with internal regulators used (see Figure 12): and in the dual supply scheme (see Figure 13). Three measurements are given: - - - The RTC is disabled, only the consumption of the LPVREG and RSM remain (almost no leakage currents) The RTC is running, clocked by a standard 32.768 kHz crystal. The RTC is running, clocked by the internal Low Power RC oscillator (LPOSC) In SLOW-WFI mode: In STOP mode: In STANDBY mode: STANDBY mode is only supported in the single supply scheme (see Figure 12) 38/71 STR750F Subject to general operating conditions for VDD_IO, and TA Table 14. Symbol Electrical parameters Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes Para meter Conditions 3.3V 5V typ(1) typ(2) Unit Clocked by OSC4M with PLL multiplication, all peripherals enabled in the MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz fHCLK=56 MHz, fPCLK=28 MHz fHCLK=48 MHz, fPCLK=24 MHz fHCLK=32 MHz, fPCLK=32 MHz fHCLK=16 MHz, fPCLK=16 MHz Supply current in fHCLK=8 MHz, fPCLK=8 MHz RUN mode(4) Clocked by OSC4M with PLL multiplication, only EXTIT peripheral enabled in the MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz fHCLK=56 MHz, fPCLK=28 MHz fHCLK=48 MHz, fPCLK=24 MHz fHCLK=32 MHz, fPCLK=32 MHz fHCLK=16 MHz, fPCLK=16 MHz fHCLK=8 MHz, fPCLK=8 MHz Clocked by OSC4M with PLL multiplication, only EXTIT peripheral enabled in the MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz(5) Supply current in fHCLK=56 MHz, fPCLK=28 MHz(5) fHCLK=48 MHz, fPCLK=24 MHz(5) WFI mode(4) fHCLK=32 MHz, fPCLK=32 MHz(6) fHCLK=16 MHz, fPCLK= 16 MHz (6) fHCLK= 8 MHz, fPCLK= 8 MHz(6) Clocked by FREEOSC: fHCLK=fPCLK=~5 MHz, Supply current in Clocked by OSC4M: fHCLK=fPCLK=4 MHz (4) SLOW mode Clocked by LPOSC: fHCLK=fPCLK=~300 kHz (7) Clocked by OSC32K: fHCLK=fPCLK=32.768 kHz Clocked by FREEOSC: fHCLK=fPCLK=~5 MHz Supply current in Clocked by OSC4M: fHCLK=fPCLK=4 MHz SLOW-WFI Clocked by LPOSC: fHCLK=fPCLK=~300 kHz (4) (7) mode Clocked by OSC32K: fHCLK=fPCLK=32.768 kHz 1. Typical data based on TA=25 C and VDD_IO=3.3V. 2. Typical data based on TA=25 C and VDD_IO=5.0V. 80 75 65 59 34 20 82 77 67 61 37 22 mA 65 60 54 42 22 16 67 62 55 44 24 18 mA IDD (3) 62 59 53 22 13 10 9 8 3.65 3.5 3.5 3.1 1.15 0.98 63 60 54 23 15 11 10 9 3.9 4.2 4.0 3.75 1.65 1.5 mA mA mA 3. The conditions for these consumption measurements are described at the beginning of Section 3.3.4 on page 35. 4. Single supply scheme see Figure 14. 5. Parameter setting BURST=1, WFI_FLASHEN=1 6. Parameter setting BURST=0, WFI_FLASHEN=0 7. Parameter setting WFI_FLASHEN=0, OSC4MOFF=1 39/71 Electrical parameters Table 15. STR750F Dual supply supply typical power consumption in Run, WFI, Slow and Slow-WFI modes To calculate the power consumption in Dual supply mode, refer to the values given in Table 14. and consider that this consumption is split as follows: IDD(single supply)~IDD(dual supply)= IDD_V18 + IDD(VDD_IO) For 3.3V range: IDD(VDD_IO) ~ 1 to 2 mA For 5V range: IDD(VDD_IO) ~ 2 to 3 mA Therefore most of the consumption is sunk on the V18 power supply This formula does not apply in STOP and STANDBY modes, refer to Table 16. Subject to general operating conditions for VDD_IO, and TA Table 16. Symbol Typical power consumption in STOP and STANDBY modes Parameter Conditions LP_PARAM bits: ALL OFF(5) LP_PARAM bits : MVREG ON, OSC4M OFF, FLASH OFF(6) LP_PARAM bits: MVREG ON, OSC4M ON , FLASH OFF(6) LP_PARAM bits: MVREG ON, OSC4M OFF, FLASH ON (6) LP_PARAM bits: MVREG ON, OSC4M ON, FLASH ON (6) 3.3V Typ(1) 12 130 1950 630 2435 5 <1 410 1475 550 <1 910 1475 11 14 5V Typ(2) 15 135 1930 635 2425 5 <1 410 1435 550 1 910 1445 14 18 Unit Supply current in STOP mode(4) A IDD(3) Supply current in STOP mode(7) LPPARAM bits: ALL OFF, with V18=1.8 V LP_PARAM bits: OSC4M ON, FLASH OFF LP_PARAM bits: OSC4M OFF, FLASH ON LP_PARAM bits: OSC4M ON, FLASH ON Supply current in STANDBY mode(4) RTC OFF RTC ON clocked by OSC32K IDD_V18 IDD_V33 IDD_V18 IDD_V33 IDD_V18 IDD_V33 IDD_V18 IDD_V33 A A 1. Typical data are based on TA=25C, VDD_IO=3.3 V and V18=1.8 V unless otherwise indicated in the table. 2. Typical data are based on TA=25C, VDD_IO=5.0 V and V18=1.8 V unless otherwise indicated in the table. 3. The conditions for these consumption measurements are described at the beginning of Section 3.3.4 on page 35. 4. Single supply scheme see Figure 12. 5. In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4 V, which significantly reduces the leakage currents. 6. In this mode, the whole digital circuitry is powered internally by the MVREG at 1.8 V. 7. Dual supply scheme see Figure 13. 40/71 STR750F Electrical parameters Supply and Clock manager power consumption Table 17. Symbol Supply and Clock manager power consumption Parameter Conditions(1) External components specified in: 4/8 MHz Crystal / Ceramic Resonator Oscillator (XT1/XT2) on page 45 3.3V Typ 5V Typ Unit Supply current of resonator oscillator IDD(OSC4M) in STOP or WFI mode (LP_PARAM bit: OSC4M ON) FLASH static current consumption in STOP or WFI mode (LP_PARAM bit FLASH ON) 1815 1795 IDD(FLASH) 515 515 A Main Voltage Regulator static current IDD(MVREG) consumption in STOP mode (LP_PARAM bit: MVREG ON) STOP mode includes leakage where V18 is internally set to 1.4 V STANDBY mode where V18BKP and V18 are internally set to 1.4 V and 0 V respectively 130 135 12 15 Low Power Voltage Regulator + RSM IDD(LPVREG) current static current consumption 11 14 1. Measurements performed in 3.3V single supply mode see Figure 12 41/71 Electrical parameters STR750F On-Chip peripheral power consumption Conditions: - - - VDD_IO=VDDA_ADC=VDDA_PLL=3.3 V or 5 V 10% unless otherwise specified. TA= 25 C Clocked by OSC4M with PLL multiplication, fCK_SYS=64 MHz, fHCLK=32 MHz, fPCLK=32 MHz On-Chip peripherals Parameter TIM Timer supply current (1) PWM Timer supply SSP supply current current(2) (3) Table 18. Symbol IDD(TIM) IDD(PWM) IDD(SSP) IDD(UART) IDD(I2C) IDD(ADC) IDD(USB) IDD(CAN) . Typ (3.3V and 5.0V) 0.7 1 1.3 1.6 0.3 1.2 0.90 2.8 Unit UART supply current (4) I2C supply current (5) mA ADC supply current when converting (6) USB supply current Note: VDD_IO must be 3.3 V 10% CAN supply current (8) (7) 1. Data based on a differential IDD measurement between reset configuration and timer counter running at 32 MHz. No IC/OC programmed (no I/O pads toggling) 2. Data based on a differential IDD measurement between reset configuration and PWM running at 32 MHz. This measurement does not include PWM pads toggling consumption. 3. Data based on a differential IDD measurement between reset configuration and permanent SPI master communication at maximum speed 16 MHz. The data sent is 55h. This measurement does not include the pad toggling consumption. 4. Data based on a differential IDD measurement between reset configuration and a permanent UART data transmit sequence at 1Mbauds. This measurement does not include the pad toggling consumption. 5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master communication at 100kHz (data sent equal to 55h). This measurement includes the pad toggling consumption but not the external 10kOhm external pull-up on clock and data lines. 6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions at 8 MHz in scan mode on 16 inputs configured as AIN. 7. Data based on a differential IDD measurement between reset configuration and a running generic HID application. 8. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence in loopback mode at 1MHz. This measurement does not include the pad toggling consumption. 42/71 STR750F Electrical parameters 3.3.5 Clock and timing characteristics XT1 external Clock source Subject to general operating conditions for VDD_IO, and TA. Table 19. Symbol fXT1 VXT1H VXT1L tw(XT1H) tw(XT1L) tr(XT1) tf(XT1) IL XT1 external Clock source Parameter External clock source frequency XT1 input pin high level voltage XT1 input pin low level voltage XT1 high or low time (3) XT1 rise or fall time (3) VSS VIN VDD_IO see Figure 20 0.7xVDD_IO VSS 6 ns 5 1 A Conditions(1) (2) Min Typ 4 Max 60 VDD_IO V 0.3xVDD_IO Unit MHz XTx Input leakage current 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production. 43/71 Electrical parameters STR750F XRTC1 external Clock source Subject to general operating conditions for VDD_IO, and TA. Table 20. Symbol fXRTC1 VXRTC1H VXRTC1L XRTC1 external Clock source Parameter External clock source frequency XRTC1 input pin high level voltage XRTC1 input pin low level see Figure 20 voltage 0.7xVDD_IO VSS 990 ns 5 VSSVINVDD_I O Conditions(1) Min Typ 32.768 Max 500 VDD_IO Unit kHz V 0.3xVDD_IO tw(XRTC1H) XRTC1 high or low time(2) tw(XRTC1L) tr(XRTC1) tf(XRTC1) IL XRTC1 rise or fall time(2) XRTCx Input leakage current 1 A 1. Data based on typical application software. 2. Data based on design simulation and/or technology characteristics, not tested in production. Figure 20. Typical application with an external Clock source 90% VXT1H 10% VXT1L tr(XT1) tf(XT1) tw(XT1H) tw(XT1L) TXT1 XT2 EXTERNAL CLOCK SOURCE hi-Z XT1 IL fOSC4M STR750 44/71 STR750F Electrical parameters 4/8 MHz Crystal / Ceramic Resonator Oscillator (XT1/XT2) The STR750 system clock or the input of the PLL can be supplied by a OSC4M which is a 4 MHz clock generated from a 4 MHz or 8 MHz crystal or ceramic resonator. If using an 8 MHz oscillator, software set the XTDIV bit to enable a divider by 2 and generate a 4 MHz OSC4M clock. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Table 21. Symbol 4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2)(1) Parameter Conditions 4 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV=0 or 8 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV=1 200 Min Typ Max Unit fOSC4M Oscillator frequency 4 MHz RF CL1(2) CL2 i2 Feedback resistor Recommended load capacitance versus equivalent RS=200 serial resistance of the crystal or (3) ceramic resonator (RS) XT2 driving current VDD_IO=3.3 V or 5.0 V 240 270 k 60 pF 425 1 A ms tSU(OSC4M)(4) Startup time at VDD_IO power-up 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(OSC4M) is the typical start-up time measured from the moment VDD_IO is powered (with a quick VDD_IO ramp-up from 0 to 3.3V (<50s) to a stabilized 4MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer. Figure 21. Typical application with a 4 or 8 MHz crystal or ceramic resonator XTDIV WHEN RESONATOR WITH INTEGRATED CAPACITORS CL1 XT1 LINEAR AMPLIFIER /2 FEEDBACK LOOP fOSC4M RESONATOR RF CL2 XT2 VDD/2 Ref i2 STR75X 45/71 Electrical parameters STR750F OSC32K crystal / ceramic resonator oscillator The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator oscillator. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Table 22. Symbol fOSC32K RF CL1 CL2 i2 OSC32K crystal / ceramic resonator oscillator Parameter Oscillator Frequency Feedback resistor VDD_IO=3.3 V VDD_IO=5.0 V Recommended load capacitance versus equivalent serial resistance of RS=TBD the crystal or ceramic resonator (RS)(1) XT2 driving current VDD_IO=3.3 V or 5.0 V VIN=VSS VDD_IO is stabilized 270 TBD TBD Conditions Min Typ 32.768 310 TBD 370 k TBD TBD pF Max Unit kHz 160 2.5 250 A s tSU(OSC32K)(2) startup time 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details 2. tSU(OSC32K) is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer Figure 22. Typical application with a 32.768 kHz crystal or ceramic resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS i2 FEEDBACK LOOP CL1 XRTC1 fOSC32K CL2 32 kHz RESONATOR XRTC2 RF STR750 PLL Characteristics PLL Jitter Terminology Self-referred single period jitter (period jitter) Period Jitter is defined as the difference of the maximum period (Tmax) and minimum period (Tmin) at the output of the PLL where Tmax is the maximum time difference between 2 consecutive clock rising edges and Tmin is the minimum time difference between 2 consecutive clock rising edges. See Figure 23 Self-referred long term jitter (N period jitter) Self-referred long term Jitter is defined as the difference of the maximum period (Tmax) and minimum period (Tmin) at the output of the PLL where Tmax is the maximum time 46/71 STR750F Electrical parameters difference between N+1 consecutive clock rising edges and Tmin is the minimum time difference between N+1 consecutive clock rising edges. N should be kept sufficiently large to have a long term jitter (ex: thousands). For N=1, this becomes the single period jitter. See Figure 23 Cycle-to-cycle jitter (N period jitter) This corresponds to the time variation between adjacent cycles over a random sample of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1 to N. See Figure 24 Figure 23. Self-referred jitter (single and long term) n IDEAL CK_PLL T n+1 --n+N ACTUAL CK_PLL single period jitter trigger point long term jitter Figure 24. Cycle-to-cycle jitter n IDEAL CK_PLL T n+1 n+2 --n+N ACTUAL CK_PLL Tcycle 1 Tcycle 2 Tcycle N-1 47/71 Electrical parameters STR750F PLL characteristics Subject to general operating conditions for VDD_IO, and TA. Table 23. Symbol PLL characteristics Value Parameter PLL input clock Test Conditions Min Typ 4.0 40 fPLL_INx 24 When PLL operates (locked) 336 60 165 960 300 fPLL_IN = 4 MHz(4) VDD_IO is stable fPLL_IN = 4 MHz(4) VDD_IO is stable +/-250 +/-2.5 +/-500 Max(1) Unit MHz % MHz MHz s ps ns ps fPLL_IN fPLL_OUT fVCO tLOCK tJITTER1(2)(3) tJITTER2(2)(3) tJITTER3(2)(3) PLL input clock duty cycle PLL multiplier output clock VCO frequency range PLL lock time Single period jitter (+/-3 peak to peak) Long term jitter (+/-3 peak to peak) Cycle to cycle jitter (+/-3 peak fPLL_IN = 4 MHz(4) VDD_IO is stable to peak) 1. Data based on product characterisation, not tested in production. 2. Refer to jitter terminology in : PLL Characteristics on page 46 for details on how jitter is specified. 3. The jitter specification holds true only up to 50mV (peak-to-peak) noise on VDDA_PLL and V18 supplies. Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter. 4. The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described in: PLL Characteristics on page 46. Internal RC Oscillators (FREEOSC & LPOSC) Subject to general operating conditions for VDD_IO, and TA. Table 24. Symbol fCK_FREEOSC fCK_LPOSC Internal RC Oscillators (FREEOSC & LPOSC) Parameter FREEOSC Oscillator Frequency LPOSC Oscillator Frequency Conditions Min 3 150 Typ 5 300 Max 8 500 Unit MHz kHz 48/71 STR750F Electrical parameters 3.3.6 Memory characteristics Flash memory Subject to general operating conditions for VDD_IO and V18, TA = -40 to 105 C unless otherwise specified. Table 25. Symbol tPW tPDW tPB0 tPB1 tES tES tES tES tRPD tPSL tESL Flash memory characteristics Value Parameter Word Program Double Word Program Bank 0 Program (256K) Bank 1 Program (16K) Sector Erase (64K) Sector Erase (8K) Bank 0 Erase (256K) Bank 1 Erase (16K) Recovery when disabled Program Suspend Latency Erase Suspend Latency Single Word programming of a checker-board pattern Single Word programming of a checker-board pattern Not preprogrammed (all 1) Preprogrammed (all 0) Not preprogrammed (all 1) Preprogrammed (all 0) Not preprogrammed (all 1) Preprogrammed (all 0) Not preprogrammed (all 1) Preprogrammed (all 0) Test Conditions Typ 35 60 2 125 1.54 1.176 392 343 8.0 6.6 0.9 0.8 4.9(2) 224(2) 2.94(2) 2.38(2) 560(2) 532(2) 13.7 11.2 1.5 1.3 20 10 300 Max(1) Unit s s s ms s ms s s s s s 1. Data based on characterisation not tested in production 2. 10K program/erase cycles. Table 26. Symbol Flash memory endurance and data retention Value Parameter Conditions Min(1) 10 100 TA=85 C Min time from Erase Resume to next Erase Suspend 20 20 Unit Typ Max kcycles kcycles Years ms NEND_B0 Endurance (Bank 0 sectors) NEND_B1 Endurance (Bank 1 sectors) YRET tESR Data Retention Erase Suspend Rate 1. Data based on characterisation not tested in production. 49/71 Electrical parameters STR750F 3.3.7 EMC characteristics Susceptibilitytests are performed on a sample basis during product characterization. Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 27. Symbol EMC characteristics Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Conditions VDD_IO=3.3 V or 5 V, TA=+25 C, fCK_SYS=32 MHz conforms to IEC 1000-4-2 Level/ Class Class A VFESD VEFTB Fast transient voltage burst limits to be applied VDD_IO=3.3 V or 5 V, through 100pF on VDD and VSS pins to induce TA=+25 C, fCK_SYS=32 MHz a functional disturbance conforms to IEC 1000-4-4 Class A 50/71 STR750F Electrical parameters Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 28. EMI characteristics Conditions Flash devices: VDD_IO=3.3 V or 5 V, TA=+25 C, LQFP64 package conforming to SAE J 1752/3 Monitored Frequency Band 0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level Max vs. [fOSC4M/fHCLK] Unit 4/32MHz 22 31 19 >4 4/60MHz 26 26 23 >4 dBV Symbo Parameter l SEMI Peak level Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. Table 29. Symbol VESD(HBM) VESD(MM) VESD(CDM) Absolute maximum ratings Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Electro-static discharge voltage (Charge Device Model) TA=+25 C Conditions Maximum value(1) 2000 200 750 V Unit 1. Data based on product characterisation, not tested in production. 51/71 Electrical parameters STR750F Static and dynamic latch-up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical sensitivities Parameter Static latch-up class TA=+25 C TA=+85 C TA=+105 C VDD= 5.5 V, fOSC4M=4 MHz, fCK_SYS=32 MHz, TA=+25 C Conditions Class(1) Class A Table 30. Symbol LU DLU Dynamic latch-up class Class A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 52/71 STR750F Electrical parameters 3.3.8 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD_IO and TA unless otherwise specified. Table 31. General characteristics I/O static characteristics Symbol VIL VIH Vhys IINJ(PIN) IINJ(PIN (2) Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis(1) Injected Current on any I/O pin Total injected current (sum of all I/O and control pins) Input leakage current on robust pins Input leakage current(3) Conditions Min Typ Max Unit 0.8 V TTL ports 2 400 4 mA 25 mV See Section 3.3.12 on page 64 VSSVINVDD_IO Floating input mode VIN=VSS VDD_IO=3.3 V VDD_IO=5 V VDD_IO=3.3 V VDD_IO=5 V 50 20 30 20 200 95 58 80 50 5 2 200 150 180 120 1 A k k k k pF TAP B Ilkg IS RPU Static current consumption(4) Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(5) I/O pin capacitance External interrupt/wake-up lines pulse time(6) RPD CIO tw(IT)in VIN=VDD_IO 1. Hysteresis voltage between Schmitt trigger switching levels. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD_IO while a negative injection is induced by VIN Electrical parameters Figure 25. Connecting unused I/O pins VDD 10k STR750F STR7XXX UNUSED I/O PORT 10k UNUSED I/O PORT STR7XXX Output driving current The GP I/Os have different drive capabilities: O2 outputs can sink or source up to +/-2 mA. O4 outputs can sink or source up to +/-4 mA. outputs can sink or source up to +/-8 mA or can sink +20 mA (with a relaxed VOL). In the application, the user must limit the number of I/O pins which can drive current to respect the absolute maximum rating specified in Section 3.2.2 : The sum of the current sourced by all the I/Os on VDD_IO, plus the maximum RUN consumption of the MCU sourced on VDD_IO, can not exceed the absolute maximum rating IVDD_IO. The sum of the current sunk by all the I/Os on VSS_IO plus the maximum RUN consumption of the MCU sunk on VSS_IO can not exceed the absolute maximum rating IVSS_IO. Subject to general operating conditions for VDD_IO and TA unless otherwise specified. 54/71 STR750F Table 32. Output driving current I/O Output Drive characteristics for VDD_IO = 3.0 to 3.6 V and EN33 bit =1 or VDD_IO = 4.5 to 5.5 V and EN33 bit =0 I/O Symbol Type VOL(1) O2 VOH(2) VOL(1) O4 VOH(2) Parameter Conditions Electrical parameters Min Max Unit Output low level voltage for a standard I/O pin when 8 pins are sunk at same IIO=+2 mA time Output high level voltage for an I/O pin I =-2 mA when 4 pins are sourced at same time IO Output low level voltage for a standard I/O pin when 8 pins are sunk at same IIO=+4 mA time Output high level voltage for an I/O pin I =-4 mA when 4 pins are sourced at same time IO Output low level voltage for a standard I/O pin when 8 pins are sunk at same IIO=+8 mA time VDD_IO-0.8 VDD_IO-0.8 0.4 0.4 V 0.4 VOL(1) O8 IIO=+20 mA, Output low level voltage for a high sink T 85C A I/O pin when 4 pins are sunk at same T 85C A time IIO=+8 mA Output high level voltage for an I/O pin I =-8 mA when 4 pins are sourced at same time IO VDD_IO-0.8 1.3 1.5 0.4 VOH(2) 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 3.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS_IO. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 3.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD_IO. 55/71 Electrical parameters STR750F Output speed Subject to general operating conditions for VDD_IO and TA unless otherwise specified. Table 33. Output speed I/O dynamic characteristics for VDD_IO = 3.0 to 3.6V and EN33 bit =1 or VDD_IO = 4.5 to 5.5V and EN33 bit =0 I/O Type Symbol Parameter Conditions CL=50 pF CL=50 pF Between 10% and 90% 30 CL=50 pF CL=50 pF Between 10% and 90% 12 CL=50pF CL=50 pF Between 10% and 90% 6 40 6 ns MHz 25 12 ns MHz Min Typ Max Unit 10 30 ns MHz Fmax(IO)out Maximum Frequency(1) O2 tf(IO)out tr(IO)out Output high to low level fall time(2) Output low to high level rise time(2) Fmax(IO)out Maximum Frequency(1) O4 tf(IO)out tr(IO)out Output high to low level fall time(2) Output low to high level rise time(2) Fmax(IO)out Maximum Frequency(1) O8 tf(IO)out tr(IO)out Output high to low level fall time(2) Output low to high level rise time(2) 1. The maximum frequency is defined as described in Figure 26. 2. Data based on product characterisation, not tested in production. Figure 26. I/O output speed definition 90% 50% 10% 10% 50% 90% EXTERNAL OUTPUT ON 50pF tr(IO)out T tr(IO)out Maximum frequency is achieved if (tr + tf) (2/3)T and if the duty cycle is (45-55%) when loaded by 50pF 56/71 STR750F Electrical parameters NRSTIN and NRSTOUT pins NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present which is the same as RPU (see : General characteristics on page 53) NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that it works only as an open-drain (the P-MOS is de-activated). A permanent pull-up is present which is the same as RPU (see : General characteristics on page 53) Subject to general operating conditions for VDD_IO and TA unless otherwise specified. Table 34. NRSTIN and NRSTOUT pins Symbol VIL(NRSTIN) VIH(NRSTIN) Vhys(NRSTIN) VOL(NRSTIN) RPU(NRSTIN) Parameter NRSTIN Input low level voltage(1) NRSTIN Input high level voltage(1) NRSTIN Schmitt trigger voltage hysteresis(2) NRSTOUT Output low level voltage(3) NRSTIN Weak pull-up equivalent resistor(4) Generated reset pulse duration (visible at NRSTOUT pin)(5) External reset pulse hold time at NRSTIN pin(6) IIO=+2 mA VIN=VSS VDD_IO=3.3 V VDD_IO=5 V 25 20 15 20 1 50 31 20 2 400 0.4 100 100 mV V k k s s s Conditions Min Typ 1) Max Unit 0.8 V tw(RSTL)out Internal reset source At VDD_IO power-up(5) When VDD_IO is established(5) The time between two spikes must be higher than 1/2 of the spike duration. th(RSTL)in tg(RSTL)in maximum negative spike duration filtered at NRSTIN pin(7) 150 ns 1. Data based on product characterisation, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 3.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. The RPU pull-up equivalent resistor are based on a resistive transistor 5. To guarantee the reset of the device, a minimum pulse of 15 s has to be applied to the internal reset. At VDD_IO power-up, the built-in reset stretcher may not generate the 15 s pulse duration while once VDD_IO is established, an external reset pulse will be internally stretched up to 15 s thanks to the reset pulse stretcher. 6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments. 7. In fact the filter is made to ignore all incoming pulses with short duration: - all negative spikes with a duration less than 150 ns are filtered - all trains of negative spikes with a ratio of 1/2 are filtered. This means that all spikes with a maximum duration of 150 ns with minimum interval between spikes of 75 ns are filtered. Data guaranteed by design, not tested in production. 57/71 Electrical parameters Figure 27. Recommended NRSTIN pin protection VDD_IO STR750F RPU NRSTOUT TO RESET OTHER CHIPS Filter INTERNAL RESET WATCHDOG RESET SOFTWARE RESET RSM RESET PULSE GENERATOR VDD_IO STR7X RPU EXTERNAL RESET CIRCUIT 0.01F NRSTIN Filter 1. The user must ensure that the level on the NRSTIN pin can go below the VIL(NRSTIN) max. level specified in NRSTIN and NRSTOUT pins on page 57. Otherwise the reset will not be taken into account internally. 58/71 STR750F Electrical parameters 3.3.9 TB and TIM timer characteristics Subject to general operating conditions for VDD_IO, fCK_SYS, and TA unless otherwise specified. Refer to Section 3.3.8: I/O port pin characteristics on page 53 for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 35. TB and TIM timers Symbol tw(ICAP)in Parameter Input capture TIM0,1,2 pulse time fCK_TIM(MAX) = fCK_SYS TB tres(TIM) Timer resolution time(1) fCK_TIM = fCK_SYS = 60 MHz fCK_TIM(MAX) = fCK_SYS TIM0,1,2 f CK_TIM = fCK_SYS = 60MHz Timer fCK_TIM(MAX) = fCK_SYS external clock TIM0,1,2 f CK_TIM = fCK_SYS = frequency on 60 MHz TI1 or TI2 Timer resolution 1 fCK_TIM = fCK_SYS = 60 MHz 0.0166 1 fCK_TIM = fCK_SYS = 60 MHz 0.0166 Conditions Min 2 1 16.6(1) 1 16.6(1) 0 0 fCK_TIM/4 15 16 65536 1092 65536 1092 Typ Max Unit tCK_TIM tCK_TIM ns tCK_TIM ns MHz MHz bit tCK_TIM s tCK_TIM s fEXT ResTIM 16-bit Counter clock TB period when tCOUNTER internal clock is selected (16-bit TIM0,1,2 Prescaler) 65536x65536 tCK_TIM TB Maximum tMAX_COUNT Possible Count fCK_TIM = fCK_SYS = 60 MHz 71.58 s 65536x65536 tCK_TIM TIM0,1,2 f CK_TIM = fCK_SYS = 60 MHz 71.58 s 1. Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to I/O pin, described in : Output speed on page 56. 59/71 Electrical parameters STR750F Table 36. PWM Timer (PWM) Symbol Parameter Conditions fCK_TIM(MAX) = fCK_SYS tres(PWM) ResPWM VOS(1) PWM resolution time fCK_TIM = fCK_SYS = 60 MHz Min 1 16.6(1) 16 VDD_IO=3.3 V, Res=16-bits VDD_IO=5.0 V, Res=16-bits 1 fCK_TIM=60 MHz 0.0166 50(1) 76 (1) Typ Max Unit tCK_TIM ns bit V V PWM resolution PWM/DAC output step voltage Timer clock period when internal clock is selected 65536 1087 tCK_TIM s tCOUNTER Maximum Possible tMAX_COUNT Count 65536x t 65536 CK_TIM fCK_TIM = fCK_SYS = 60 MHz 71.58 s 1. Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to an I/O pin, as described in : Output speed on page 56. 60/71 STR750F Electrical parameters 3.3.10 Communication interface characteristics I2C - Inter IC control interface Subject to general operating conditions for VDD_IO, fPCLK, and TA unless otherwise specified. The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Restriction: The I/O pins which SDA and SCL are mapped to are not "True" OpenDrain: when configured as open-drain, the PMOS connected between the I/O pin and VDD_IO is disabled, but it is still present. Also, there is a protection diode between the I/O pin and VDD_IO. Consequently, when using this I2C in a multi-master network, it is not possible to power off the STR7x while some another I2C master node remains powered on: otherwise, the STR7x will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 37. Symbol SDA and SCL characteristics Parameter Standard mode I2C Min(2) Max(2) Fast mode I2C(1) Unit Min(2) 1.3 0.6 100 0(4) 1000 300 4.0 4.7 4.0 4.7 400 20+0.1Cb 20+0.1Cb 0.6 0.6 0.6 1.3 400 900(3) 300 300 s s s pF ns Max(2) s tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time 4.7 4.0 250 0(3) tw(STO:STA) STOP to START condition time (bus free) Cb Capacitive load for each bus line 1. fPCLK, must be at least 8 MHz to achieve max fast I2C speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 61/71 Electrical parameters Figure 28. Typical application with I2C bus and timing diagram VDD 4.7k I2C BUS 4.7k VDD 100 100 SDA SCL STR750F STRT75X REPEATED START START tsu(STA) SDA tw(STO:STA) START tf(SDA) SCL tr(SDA) tsu(SDA) th(SDA) STOP th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 62/71 STR750F Electrical parameters 3.3.11 USB characteristics The USB interface is USB-IF certified (Low Speed and High Speed). Table 38. USB characteristics USB DC Electrical Characteristics Symbol Parameter Conditions Input Levels VDI VCM VSE Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels VOL VOH Static Output Level Low Static Output Level High RL of 1.5 k to 3.6V(3) RL of 15 k to VSS(3) 2.8 0.3 V 3.6 I(DP, DM) Includes VDI range 0.2 0.8 1.3 2.5 2.0 V Min.(1)(2) Max.(1)(2) Unit 1. All the voltages are measured from the local ground potential. 2. It is important to be aware that the DP/DM pins are not 5 V tolerant. As a consequence, in case of a a shortcut with Vbus (typ: 5.0V), the protection diodes of the DP/DM pins will be direct biased . This will not damage the device if not more than 50 mA is sunk for longer than 24 hours but the reliability may be affected. 3. RL is the load connected on the USB drivers Figure 29. USB: data signal rise and fall time Differential Data Lines VCRS Crossover points VSS tf tr Table 39. Symbol USB: Full speed electrical characteristics Parameter Conditions Driver characteristics: Min Max Unit tr tf trfm VCRS Rise time Fall (1) CL=50 pF CL=50 pF tr/tf 4 4 90 1.3 20 20 110 2.0 ns ns % V Time1) Rise/ Fall Time matching Output signal Crossover Voltage 1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 63/71 Electrical parameters STR750F 3.3.12 10-bit ADC characteristics Subject to general operating conditions for VDDA_ADC, fPCLK, and TA unless otherwise specified. Table 40. Symbol fADC VAIN RAIN CAIN 10-bit ADC characteristics Parameter ADC clock frequency Conversion voltage range External input impedance External capacitor on analog input +400 A injected on any pin -400 A injected on any pin except specific adjacent pins in Table 41 -400A injected on specific adjacent pins in Table 41 TBD(2)(3)(4) pF 1 A Conditions Min 0.4 VSSA_ADC Typ(1) Max 8 VDDA_ADC Unit MHz V k 1 A Ilkg Induced input leakage current 40 A CADC tCAL Internal sample and hold capacitor Calibration Time fCK_ADC=8 MHz 3.5 725.25 5802 pF s 1/fADC s 1/fADC mA tCONV Total Conversion time (including sampling time) fCK_ADC=8 MHz 3.75 30 (11 for sampling + 19 for Successive Approximation) IADC Sunk on VDDA_ADC 3.7 1. Unless otherwise specified, typical data are based on TA=25C. They are given only as design guidelines and are not tested. 2. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies 8 MHz. 4. Calibration is needed once after each power-up. 64/71 STR750F Electrical parameters ADC Accuracy vs. Negative Injection Current Injecting negative current on specific pins listed in Table 41 (generally adjacent to the analog input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed. It is recommended to add a Schottky diode (pin to ground) to pins which may potentially inject negative current. Table 41. List of adjacent pins Related adjacent pins None None P0.11 P0.18 and P0.16 P0.24 None P2.04 P1.11 and P0.26 P0.30 and P0.28 None P1.05 P1.04 and P1.13 P2.17 and P0.27 None P1.14 and P1.01 None Analog input a AIN1/P0.03 AIN2/P0.12 AIN3/P0.17 AIN4/P0.19 AIN5/P0.22 AIN6/P0.23 AIN7/P0.27 AIN8/P0.29 AIN9/P1.04 AIN10/P1.06 AIN11/P1.08 AIN12/P1.11 AIN13/P1.12 AIN14/P1.13 AIN15/P1.14 Figure 30. Typical application with ADC VDD VT 0.6V RAIN VAIN CAIN VT 0.6V IL 1A AINx STR75XX 2k(max) 10-Bit A/D Conversion CADC 3.2pF Analog Power Supply and Reference Pins The VDDA_ADC and VSSA_ADC pins are the analog power supply of the A/D converter cell. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see : General PCB Design Guidelines on page 66). 65/71 Electrical parameters STR750F General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1 F and optionally, if needed 10 pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10 F capacitor close to the power source (see Figure 31). The analog and digital power supplies should be connected in a star network. Do not use a resistor, as VDDA_ADC is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the A/D input being converted. Software Filtering of Spurious Conversion Results For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques. Figure 31. Power supply filtering STR75XX 1 to 10F STR7 DIGITAL NOISE FILTERING 0.1F VSS VDD_IO VDD POWER SUPPLY SOURCE (3.3V or 5.0V) EXTERNAL NOISE FILTERING 0.1F VDDA_ADC VSSA_ADC 66/71 STR750F Table 42. ADC accuracy Electrical parameters ADC Accuracy with fCK_SYS = 20 MHz, fADC=8 MHz, RAIN < 10 k This assumes that the ADC is calibrated(1) Symbol |ET| Parameter Total unadjusted error (2) (3) Conditions VDDA_ADC=3.3 V VDDA_ADC=5.0 V Offset error(2) (3) VDDA_ADC=3.3 V VDDA_ADC=5.0 V Gain Error (2) (3) VDDA_ADC=3.3 V VDDA_ADC=5.0 V Differential linearity error(2) (3) VDDA_ADC=3.3 V VDDA_ADC=5.0 V Integral linearity error (2) (3) VDDA_ADC=3.3 V VDDA_ADC=5.0 V Typ 1 1 0.15 0.15 -0.8 -0.8 0.7 0.7 0.6 0.6 Max 1.2 1.2 0.5 0.5 -0.2 LSB -0.2 0.9 0.9 0.8 0.8 Unit |EO| EG |ED| |EL| 1. Calibration is needed once after each power-up. 2. Refer to ADC Accuracy vs. Negative Injection Current on page 65 3. ADC Accuracy vs. MCO (Main Clock Output): the ADC accuracy can be significantly degraded when activating the MCO on pin P0.01 while converting an analog channel (especially those which are close to the MCO pin). To avoid this, when an ADC conversion is launched, it is strongly recommended to disable the MCO. Figure 32. ADC accuracy characteristics Digital Result ADCDR 1023 1022 1021 1LSB IDEAL V -V DDA SSA = ---------------------------------------EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 1024 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 5 6 7 Vin 1021 1022 1023 1024 VDDA 67/71 Package characteristics STR750F 4 4.1 Package characteristics Package mechanical data Figure 33. 64-Pin Low Profile Quad Flat Package (10x10) Dim. D D1 A1 A A2 mm Min 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006 A A1 A2 b 1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008 b c D D1 E1 E e E E1 e c L L1 N L1 L Number of Pins Figure 34. 100-Pin Low Profile Flat Package (14x14) D D1 A A2 Dim. A mm Min 0.05 1.35 0.17 0.09 16.00 14.00 16.00 14.00 0.50 0 0.45 3.5 0.60 1.00 100 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006 A1 A1 A2 b 1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.630 0.551 0.630 0.551 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008 b C D e E1 E D1 E E1 e L c L1 L h L1 N Number of Pins 68/71 STR750F Package characteristics Figure 35. 64-Low Profile Fine Pitch Ball Grid Array Package mm Min 1.210 0.270 1.120 Typ Max Min 0.011 0.044 1.700 0.048 inches Typ Max 0.067 Dim. A A1 A2 b D D1 E E1 e f ddd N 0.450 0.500 0.550 0.018 0.020 0.022 7.750 8.000 8.150 0.305 0.315 0.321 5.600 5.600 0.220 0.220 7.750 8.000 8.150 0.305 0.315 0.321 0.720 0.800 0.880 0.028 0.031 0.035 1.050 1.200 1.350 0.041 0.047 0.053 0.120 Number of Pins 64 0.005 Figure 36. 100-Low Profile Fine Pitch Ball Grid Array Package Dim. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff N 0.45 0.50 7.20 7.20 0.80 1.40 0.12 0.15 0.08 Number of Balls 100 0.270 1.085 0.30 0.80 mm Min Typ Max 1.700 0.011 0.043 0.012 0.031 0.55 0.018 0.020 0.022 0.283 0.283 0.031 0.055 0.005 0.006 0.003 Min inches Typ Max 0.067 9.85 10.00 10.15 0.388 0.394 0.40 9.85 10.00 10.15 0.388 0.394 0.40 Figure 37. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print Dpad Dsm 69/71 Package characteristics STR750F 4.2 Thermal characteristics The average chip-junction temperature, TJ must never exceed 125 C. The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA)(1) Where: - - - - - TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power. PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the applications PI/O < PINT and may be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) (2) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2(3) where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. Thermal characteristics Parameter Thermal Resistance Junction-Ambient LQFP 100 - 14 x 14 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient LFBGA 64 - 8 x 8 x 1.7mm Thermal Resistance Junction-Ambient LFBGA 100 - 10 x 10 x 1.7mm Value 46 45 58 41 Unit C/W C/W C/W C/W Table 43. Symbol JA JA JA JA 70/71 STR750F Order codes 5 Order codes Table 44. Order codes Flash Prog. Memory Partnumber (Bank 0) Kbytes STR750FV0T6 STR750FV1T6 STR750FV2T6 STR750FV2H6(1) STR751FR0T6 STR751FR1T6 STR751FR2T6 STR751FR2H6(1) STR752FR0T6 STR752FR1T6 STR752FR2T6 STR752FR2H6(1) STR752FR0T7 STR752FR1T7 STR752FR2T7 STR752FR2H7(1) STR755FR0T6 STR755FR1T6 STR755FR2T6 STR755FR2H6 (1) Package CAN Periph USB Periph Temp. Range 64 128 256 256 64 128 256 256 64 128 256 256 64 128 256 256 64 128 256 256 64 128 256 256 LFBGA100 10x10 LQFP100 14x14 LFBGA64 8x8 -40 to +85C LQFP64 10x10 LFBGA64 8x8 LQFP64 10x10 Yes -40 to +105C LFBGA64 8x8 LQFP64 10x10 Yes -40 to +85C LFBGA64 8x8 LQFP64 10x10 Yes -40 to +85C LFBGA100 10x10 LQFP100 14x14 Yes Yes -40 to +85C STR755FV0T6 STR755FV1T6 STR755FV2T6 STR755FV2H6 (1) 1. For other memory sizes, contact sales office. 71/71 Revision history STR750F 6 Revision history Table 45. Date 25-Sep-2006 30-Oct-2006 Revision history Revision 1 2 Initial release Added power consumption data for 5V operation in Section 3 Description of Changes 72/71 STR750F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 71/71 |
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